Bookcover of Variability Tolerant Networks on Chip
Booktitle:

Variability Tolerant Networks on Chip

LAP LAMBERT Academic Publishing (2015-04-29 )

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ISBN-13:

978-3-659-66090-0

ISBN-10:
3659660906
EAN:
9783659660900
Book language:
English
Blurb/Shorttext:
NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for different technology nodes and NoC size. Finally, variability-aware routing algorithms make use of process variability link failure probability and adapt routing to reduce the NoC failure rate.
Publishing house:
LAP LAMBERT Academic Publishing
Website:
https://www.lap-publishing.com/
By (author) :
Eman Gawish
Number of pages:
132
Published at:
2015-04-29
Stock:
Available
Category:
Electronics, electro-technology, communications technology
Price:
61.90 €
Keywords:
Process Variations, Routing Algorithms, Networks-on-Chip (NoC), Voltage mode interconnect, Current mode interconnect, NoC topologies

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