Bookcover of Low Power Latch Designs in Subthreshold Region
Booktitle:

Low Power Latch Designs in Subthreshold Region

Designs for Portable applications

LAP LAMBERT Academic Publishing (2012-06-18 )

Books loader

Omni badge eligible for voucher
ISBN-13:

978-3-659-16061-5

ISBN-10:
365916061X
EAN:
9783659160615
Book language:
English
Blurb/Shorttext:
In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.
Publishing house:
LAP LAMBERT Academic Publishing
Website:
https://www.lap-publishing.com/
By (author) :
Krishna Gopal Sharma, Abhilasha Choudhary, Tripti Sharma
Number of pages:
80
Published at:
2012-06-18
Stock:
Available
Category:
Electronics, electro-technology, communications technology
Price:
49.00 €
Keywords:
delay, Low Power, Portable, Power Consumption, Latch, 8T, 6T

Books loader

Newsletter

Adyen::amex Adyen::mc Adyen::visa Adyen::cup Adyen::unionpay Paypal Wire Transfer

  0 products in the shopping cart
Edit cart
Loading frontend
LOADING