Bookcover of Design of Reconfigurable Decoder for SRAM
Booktitle:

Design of Reconfigurable Decoder for SRAM

Schematic and layout design of 5:32 bit reconfigurable decoder

LAP LAMBERT Academic Publishing (2012-05-26 )

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ISBN-13:

978-3-659-11416-8

ISBN-10:
3659114162
EAN:
9783659114168
Book language:
English
Blurb/Shorttext:
Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.
Publishing house:
LAP LAMBERT Academic Publishing
Website:
https://www.lap-publishing.com/
By (author) :
Arti Noor, Sampath Kumar V., Abhinav Vishnoi
Number of pages:
96
Published at:
2012-05-26
Stock:
Available
Category:
Electronics, electro-technology, communications technology
Price:
49.00 €
Keywords:
reconfigurable, SRAM, Decoder, 5-32-bit decoder

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