High Performance and Energy Efficient Many-core DSP
Systems
An Asynchronous Array of Simple Processors
978-3-639-09859-4
3639098595
168
2008-12-12
68.00 €
eng
https://images.our-assets.com/cover/230x230/9783639098594.jpg
https://images.our-assets.com/fullcover/230x230/9783639098594.jpg
https://images.our-assets.com/cover/2000x/9783639098594.jpg
https://images.our-assets.com/fullcover/2000x/9783639098594.jpg
This book investigates the architecture design,
physical implementation, result evaluation, and
feature analysis of a many-core processor for DSP
applications. The system is composed of a 2-D array
of simple single-issue programmable processors
interconnected by a reconfigurable mesh network, and
processors operate completely asynchronously with
respect to each other in a Globally Asynchronous
Locally Synchronous fashion. The processor is called
Asynchronous Array of simple Processors (AsAP). A
6×6 array has been fabricated in a 0.18 µm CMOS
technology. The physical design concerns timing
issues for robust implementations, and takes full
advantages of their potential scalability. Each
processor occupies 0.66 mm², is fully functional at
a clock rate of 520–540 MHz under 1.8 V, and
dissipates 94 mW while the clock is 100% active.
The system is also easily scalable, and is well-
suited to future fabrication technologies.
https://www.morebooks.shop/books/gb/published_by/vdm-verlag-dr-mueller/3/products
Hardware
https://www.morebooks.shop/store/gb/book/high-performance-and-energy-efficient-many-core-dspsystems/isbn/978-3-639-09859-4