Bookcover of FPGA Implementation of MIL-STD-1553B Bus Protocol
Booktitle:

FPGA Implementation of MIL-STD-1553B Bus Protocol

Design, Simulation and Hardware Implementation

LAP LAMBERT Academic Publishing (2013-06-13 )

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ISBN-13:

978-3-659-38419-6

ISBN-10:
3659384194
EAN:
9783659384196
Book language:
English
Blurb/Shorttext:
Modern day avionics and satellite communication systems communicate with each other using MIL-STD- 1553B bus protocol. This book aim to provide an intensive study for the software and hardware level implementation of MIL-STD-1553B bus protocol on FPGA board using a new methodology of digital phase lock loop (DPLL). The book describes the basics of bus protocol, modular level implementation of different units of protocol and software & hardware implementation issues and their solutions. ISE Xilinx Spartan 3 FPGA kit is used for the execution of different modules of protocol like UART, Bus Controller, Manchester encoder/decoder and DPLL. DPLL is used for data clock recovery from encoded Manchester data of the channel at receiver end, instead of implementing common practice of initiating a separate clock for encoded Manchester data processing. Usage of DPLL, resolves the synchronization issues, a major concern in high data rate embedded systems and increases the integrity and reliability of the system. The actual implementation of different transactions of bus i.e. BC to RT and RT to RT is discussed in detailed.
Publishing house:
LAP LAMBERT Academic Publishing
Website:
https://www.lap-publishing.com/
By (author) :
Jawad Yousaf, Iftekhar Mehmood
Number of pages:
156
Published on:
2013-06-13
Stock:
Available
Category:
Electronics, electro-technology, communications technology
Price:
61.90 €
Keywords:
MIL-STD-1553, DPLL, FPGA Board, Digital Phase Lock Loop, 1553 Transactions, BC to RT, RT to RT, Manchester Encoder, Manchester Decoder, DPLL For Clock Recovery

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