Portada del libro de PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA
Título del libro:

PVT Variation Aware Low Power Vedic Multiplier Design For DSPs on FPGA

Process Voltage Temperature Variation Using IO Standards on FPGA

LAP LAMBERT Academic Publishing (2014-11-03 )

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ISBN-13:

978-3-659-62935-8

ISBN-10:
3659629359
EAN:
9783659629358
Idioma del libro:
Inglés
Notas y citas / Texto breve:
As the communication and signal processing industries are proliferating the demand for the multipliers is continuously increasing at a rapid rate. For researchers, to develop high speed and power efficient multiplier has been a grave matter of concern. Reduction in the power consumption and delay of a multiplier circuitry is expected to cause a revolution in the field of electronics and communication.The performance of system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Hence, optimizing the speed and power consumption of the multiplier is a major design issue. There is need of development of high speed and low power multiplier for digital signal processing algorithms. From the previous research, it has been concluded that Vedic multiplier are more efficient than conventional multiplier. In this work, low power Vedic multiplier has been proposed.
Editorial:
LAP LAMBERT Academic Publishing
Sitio web:
https://www.lap-publishing.com/
Por (autor):
Kavita Goswami, Bishwajeet Pandey
Número de páginas:
104
Publicado en:
2014-11-03
Stock:
Disponible
Categoría:
Tecnología
Precio:
54.90 €
Palabras clave:
Vedic Multiplier, PVT Variation, HSTL, LVCMOS, SSTL, LVDCI IO Standards

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